(1) Field of the Invention
This invention relates to a method of fabrication used in the semiconductor integrated circuit devices, and more specifically to the formation of planarized structures of conducting copper lines and interconnects (studs) using a dual damascene process with unique techniques for removing the excess copper, such as, vapor and liquid acid etch back of copper oxides.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits CMP (Chemical Mechanical Polishing) is typically used to remove copper in a dual damascene process, whereby inlaid structures are made with insulating oxide material. The inlaid structures are filled with copper by collimated sputter deposition, for example. After metal deposition the excess copper is removed and planarized usually by CMP. Chemical and mechanical selectivities between materials are necessary, since CMP must remove the copper metal without removing large amounts of inlaid metal. The copper forms conducting lines and interconnect (plugs), which connect upper and lower interconnection layers. CMP is widely used, however it will be shown that the present invention uses acids in vapor and liquid, in combination with oxygen, to form copper oxides and said copper oxides are subsequently etched back to form planar copper structures.
U.S. Pat. No. 5,736,457 to Zhao shows a copper single and dual damascene process whereby the excess copper is exposed by a masking layer and etched back to an etch stop layer of TiN, for planarization.
U.S. Pat. No. 5,567,300 to Datta and O'Toole describes a copper electrochemical planarization process. A neutral salt solution is used and is compatible with a plating process.
U.S. Pat. No. 5,614,765 to Avanzino et al shows a self aligned via dual damascene process utilizing only one mask pattern for conducting lines and vias.
U.S. Pat. No. 5,674,787 to Zhao et al describes electroless copper deposited interconnect plugs for ULSI applications. The invention features sidewall via liners SiN or SiON. A contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer.
U.S. Pat. No. 5,585,673 to Joshi et al describes Al--Cu alloy and copper lines deposited by PVD (evaporated or sputtered) and covered with CVD W refractory metal. Capping a low resistivity metal conductor line or via with refractory metal allows for effectively using CMP because of the hard, reduced wear nature of the refractory metals.
U.S. Pat. No. 5,595,937 to Mikagi shows a trench damascene process for interconnections buried in trenches. Interconnect trench and contact hole are lined with TiN or Ti. A Cu film grown by MO-CVD, and thereafter the Cu film and TiN/Ti film on the surface of the substrate are partially removed by CMP.
U.S. Pat. No. 5,723,387 to Chen describes a self contained apparatus for multiple process step for dual copper damascene process. The patent incorporates wet processes including electroless metal plating and planarization. Exposed portions of a barrier layer are selectively removed by a wet etch.